Split gate non-volatile flash memory devices are known. FIG. 1 illustrates a 2-Gate Cell that includes two gates (word line gate WL and floating gate FG), and thus includes three terminals (word line WL, source S, and drain D). Drain D can alternately be referred to as bit line BL, and word line WL can alternately be referred to as the control gate. The floating gate FG is partially over and insulated from the source S and a portion of the channel region CR (which extends between the source S and drain D), and the word line WL is over and insulated from the other portion of the channel region CR. The floating gate FG has an upper surface terminating in a sharp edge that faces the word line WL (to facilitate erase operation). U.S. Pat. No. 5,029,130 discloses such a memory cell, which is incorporated herein by reference for all purposes.
FIG. 2 illustrates an extended source 2-Gate Cell, which is similar to the memory device of FIG. 1, except that it further includes an extended source line ESL formed over and in contact with source S. The extended source line ESL provides enhanced voltage coupling from the source S to the floating gate FG via the extended source line ESL.
FIG. 3 illustrates a 4-Gate, 5-terminal Cell, which is similar to the memory device of FIG. 1, except that it further includes an erase gate EG over and insulated from source region S, and a coupling gate CG over and insulated from the floating gate FG. The erase operation uses the upper surface edge of the floating gate FG that faces the erase gate EG. Thus, this memory cell has four gates (WL, CG, FG, EG) and 5 terminals (S, D, WL, CG, EG). U.S. Pat. Nos. 6,747,310 and 7,868,375 disclose such a memory cell, which are incorporated herein by reference for all purposes.
It is desirable to achieve the functionality and performance advantages of the 4-gate device, but with smaller device geometries and fewer masking steps during manufacturing.